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%ما هو (من)٪ 1 - تعريف
METHOD OF IMPROVING INSTRUCTION-LEVEL PARALLELISM
Instruction Prefetch Queue; Superpipelined; Deep pipelining; Pipelined CPU; Prefetch instruction queue; Superpipeline; Pipelined processor; Instruction pipeline
superpipelined
1. Traditional pipelined architectures have a single
pipeline stage for each of: instruction fetch, instruction
decode, memory read, ALU operation and memory write. A
superpipelined processor has a pipeline where each of
these logical steps may be subdivided into multiple pipeline
stages.
2. Marketese for pipelined.
Instruction pipelining
In computer science, instruction pipelining is a technique for implementing instruction-level parallelism within a single processor. Pipelining attempts to keep every part of the processor busy with some instruction by dividing incoming instructions into a series of sequential steps (the eponymous "pipeline") performed by different processor units with different parts of instructions processed in parallel.
ويكيبيديا
Instruction pipelining
In computer engineering, instruction pipelining is a technique for implementing instruction-level parallelism within a single processor. Pipelining attempts to keep every part of the processor busy with some instruction by dividing incoming instructions into a series of sequential steps (the eponymous "pipeline") performed by different processor units with different parts of instructions processed in parallel.
